By accessing all design tools in one place, engineers can complete their entire design process within the same intuitive environment and deliver high-quality products quickly.Įffortlessly create PCB designs with an intuitive interface that seamlessly connects you to every detail of the electronics design process from idea to manufacture.Ĭompile projects to create a single, cohesive model which can sit central to the design process. The world's most trusted PCB design system.Īltium Designer® offers a unified design environment, empowering engineers with a single view of every aspect of the PCB design process from schematic, to PCB layout, to design documentation. OS: Windows 64bit | Language: English | Size: 2.8 GB So I followed the “solution” and turned off the error.Altium Designer 22.6.1 Build 34 (圆4) But I think more than two different kind of these markers (one for power net and one for unused pins) create more confusion than they help. Another way would be the same approach with non-ERC markers. The official solution is to turn off this error. I stumbled across the same problem and was astonished after looking it up at the Altium website. You also mentioned the ERC “multiple net names” in the comments. (Yes, It is annoying for the first marker you create because of the large selection matrix, but once you checked the right boxes everything works as it should) I am using this method and it works fine so far. In order to get rid of the error, simply use non-ERC markers (for that net) that explicitly allow this kind of error.

That way you can easily distinguish between power and non-power nets/ports which is probably more important than direction of energy or current. So regarding your problem with the port styles for power, I would suggest using number 4. In my experience you will always get some kind ERC in Altium when dealing with hierarchical sheets (speaking from an Altium 19 perspective).

Altium designer hierarchical schematic